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tps65185 www.ti.com slvsaq8b C february 2011 C revised october 2011 pmic for e ink ? vizplex ? enabled electronic paper display check for samples: tps65185 1 features ? active discharge on all rails ? flexible power-up and power down 2345 ? single chip power management solution for sequencing e ink ? vizplex ? electronic paper displays ? integrated 10- , 3.3-v power switch for ? generates positive and negative gate and disabling system power rail to e-ink panel source driver voltages and back-plane bias from a single, low-voltage input supply ? thermistor monitoring ? supports 9.7 inch and larger panel size C C 10 c to 85 c temperature range ? 3-v to 6-v input voltage range C 1 c accuracy from 0 c to 50 c ? boost converter for positive rail base ? i 2 c serial interface ? inverting buck-boost converter for negative C slave address 0x68h rail base ? package options: ? two adjustable ldos for source driver C 48-pin, 0.5 mm pitch, supply 7 mm x 7 mm x 0.9 mm (qfn) rgz C ldo1: 15 v, 120 ma (vpos) C 48-pin, 0.4 mm pitch, C ldo2: C 15 v, 120 ma (vneg) 6 mm x 6 mm x 0.9 mm (qfn) rsl ? accurate output voltage tracking applications C vpos - vneg = 50 mv ? power supply for active matrix e ink ? ? two charge pumps for gate driver supply vizplex ? panels C cp1: 22 v, 10 ma (vddh) ? epd power supply C cp2: C 20 v, 12 ma, (vee) ? e-book readers ? adjustable vcom driver for accurate ? epson ? s1d13522 (isis) timing controller panel-backplane biasing ? epson ? s1d13521 (broadsheet) timing C user programmable default controller C 0 v to -5.11 v ? application processors with integrated or C 1.5% accuracy ( 10 mv) software timing controller ( omap ? ) C 9-bit control (10-mv nominal step size) description the tps65185 is a single-chip power supply designed to for e ink ? vizplex ? displays used in portable e-reader applications and supports panel sizes up to 9.7 inches and greater. two high efficiency dc/dc boost converters generate 16-v rails which are boosted to 22 v and C 20 v by two change pumps to provide the gate driver supply for the vizplex ? panel. two tracking ldos create the 15-v source driver supplies which support up to 120-ma of output current. all rails are adjustable through the i 2 c interface to accommodate specific panel requirements. accurate back-plane biasing is provided by a linear amplifier that can be adjusted from 0 v to -5.11 v with 9-bit control through the serial interface and can source or sink current depending on panel condition. the tps65185 supports automatic panel kickback voltage measurement which eliminates the need of manual vcom calibration in the production line. the measurement result can be stored in non-volatile memory to become the new vcom power-up default value. 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 omap is a trademark of texas instruments. 3 vizplex is a trademark of e ink corporation. 4 e ink is a registered trademark of e ink corporation. 5 epson is a registered trademark of seiko epson corporation. production data information is current as of publication date. copyright ? 2011, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
tps65185 slvsaq8b C february 2011 C revised october 2011 www.ti.com this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. description (continued) tps65185 is available in two packages, a 48-pin 7x7 mm 2 qfn with 0.5-mm pitch and a 48-pin 6x6 mm 2 qfn with 0.4-mm pitch. functional block diagram 2 submit documentation feedback copyright ? 2011, texas instruments incorporated product folder link(s): tps65185 dcdc 2 vin_p 10uf 4. 7uf vpos 10nf 2.2uf 1m 52. 3k vee_d vee_drv vee_fb 4.7uh vn_sw from battery (3.0v-6.0v) vee (-20v) vpos (15v) dcdc 1 4.7uf 2.2uh pgnd 1 vb_sw 10uf 10nf 2.2uf 1m 47.5k vddh_d vddh_drv vddh_fb from battery (3 .0 v-6 .0v) vddh (22v) vddh_ dis vddh_en vee_dis vee_en pgnd2 pgnd2 pgnd2 pgnd2 vpos_en pgnd2 vb ldo1 vee charge pump vnpbkg pgnd 2 4.7uf vpos_ dis vneg_in vddh_in vneg vneg (-15v) vneg_en ldo2 powerpad? temp sensor 43k 10k ntc ts agnd 2 adc tmst_value[7:0] 4. 7uf pgnd2 vneg_dis 4.7uf vpos_in vin 10uf vcom _pwr 4. 7uf to panel back-plane (0 to -5.11 v) from input supply (3 .0 v-6.0v) 4. 7uf vref agnd 1 dac vcom vcom[8:0] vcom _ctrl 4.7uf from uc vref 4. 7uf int _ldo int_ldo vee_in vddh charge pump 4.7uf vcom_ dis 1k 1k 1k 1k 1k 3 .3v supply from system to epd panel vin3p3 v3p3 gate driver v3p3_en 1k scl from uc from/to uc or dsp sda 10k vio pwr_good 10k vio digital core wakeup int 10k vio 10k vio from uc pwrup from uc to uc to uc dgnd 100n 100n
tps65185 www.ti.com slvsaq8b C february 2011 C revised october 2011 ordering information (1) t a package (2) orderable part number top-side marking rgz tps65185rgzr tps65185 -10 c to 85 c rsl tps65185rslr tps65185 (1) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti web site at www.ti.com . (2) package drawings, thermal data, and symbolization are available at www.ti.com/packaging . device information terminal functions (3) terminal i/o description name no. vref 1 o filter pin for 2.25-v internal reference to adc int 2 o open drain interrupt pin (active low) vneg 3 o negative supply output pin for panel source drivers vneg_in 4 i input pin for ldo2 (vneg) wake up pin (active high). pull this pin high to wake up from sleep mode. ic accepts i 2 c wakeup 5 i commands after wakeup pin is pulled high but power rails remain disabled until pwrup pin is pulled high. dgnd 6 digital ground. connect to ground plane. int_ldo 7 o filter pin for 2.7-v internal supply (3) there will be 0-ns, 93.75- s, 62.52- s of deglitch for pwrx, wakeup, and vcom_ctrl, respectively. copyright ? 2011, texas instruments incorporated submit documentation feedback 3 product folder link(s): tps65185 vddh_in C 37 n/c C 38 n/c C 39 vb_sw C 40 pgnd1 C 41 vb C 42 vpos_in C 43 vpos C 44 vin3p3 C 45 v3p3 C 46 ts C 47 agnd2 C 48 vref C 1 nint C 2 vneg C 3 vneg_in C 4 wakeup C 5 dgnd C 6 int_ldo C 7 agnd1 C 8 vneg_dis C 9 vin C 10 n/c C 11 vcom_ctrl C 12 23 C pwr_good 22 C pbkg 21 C pwrup 20 C n/c 19 C vpos_dis 18 C sda 17 C scl 16 C vcom_pwr 15 C vcom 14 C vcom_dis 13 C n/c 24 C vin_p 36 C vddh_drv 35 C vddh_dis 34 C vddh_d 33 C vddh_fb 32 C pgnd2 31 C vee_fb 30 C vee_d 29 C vee_dis 28 C vee_drv 27 C vee_in 26 C vn 25 C vn_sw rgz or rsl package (top view)
tps65185 slvsaq8b C february 2011 C revised october 2011 www.ti.com terminal i/o description name no. agnd1 8 analog ground for general analog circuitry discharge pin for vneg. connect to vneg to discharge vneg to ground whenever the vneg_dis 9 o rail is disabled. leave floating if discharge function is not desired. vin 10 i input power supply to general circuitry n/c 11 not internally connected vcom enable. pull this pin high to enable the vcom amplifier. when pin is pulled low vcom_ctrl 12 i and vn is enabled, vcom discharge is enabled. n/c 13 not internally connected discharge pin for vcom. connect to ground to discharge vcom to ground whenever vcom_dis 14 i vcom is disabled. leave floating if discharge function is not desired. vcom 15 o filter pin for panel common-voltage driver vcom_pwr 16 i internal supply input pin to vcom buffer. connect to the output of dcdc2. scl 17 i serial interface (i 2 c) clock input sda 18 i/o serial interface (i 2 c) data input/output discharge pin for vpos. connect a resistor from vpos_dis to vpos to discharge vpos_dis 19 i vpos to ground whenever the rail is disabled. leave floating if discharge function is not desired. n/c 20 not internally connected pwrup 21 i power-up pin. pull this pin high to power-up all output rails. die substrate. connect to vn (-16 v) with short, wide trace. wide copper trace will pbkg 22 improve heat dissipation. open drain power good output pin. pin is pulled low when one or more rails are disabled pwr_good 23 o or not in regulation. dcdc1, dcdc2, and vcom have no effect on this pin. vin_p 24 i input power supply to inverting buck-boost converter (dcdc2) vn_sw 25 o inverting buck-boost converter switch out (dcdc2) feedback pin for inverting buck-boost converter (dcdc2) and supply for vneg ldo and vn 26 i vee charge pump vee_in 27 i input supply pin for negative charge pump (cp2) (vee) vee_drv 28 o driver output pin for negative charge pump (cp2) discharge pin for vee. connect a resistor from vee _dis to vee to discharge vee to vee_dis 29 i ground whenever the rail is disabled. leave floating if discharge function is not desired. vee_d 30 o base voltage output pin for negative charge pump (cp2) vee_fb 31 i feedback pin for negative charge pump (cp2) pgnd2 32 power ground for cp1 (vddh) and cp2 (vee) charge pumps vddh_fb 33 i feedback pin for positive charge pump (cp1) vddh_d 34 o base voltage output pin for positive charge pump (cp1) discharge pin for vddh. connect to vddh to discharge vddh to ground whenever the vddh_dis 35 i rail is disabled. leave floating if discharge function is not desired. vddh_drv 36 o driver output pin for positive charge pump (cp1) vddh_in 37 i input supply pin for positive charge pump (cp1) n/c 38 not internally connected n/c 39 not internally connected vb_sw 40 o boost converter switch out (dcdc1) pgnd1 41 power ground for dcdc1 feedback pin for boost converter (dcdc1) and supply for vpos ldo and vddh charge vb 42 i pump vpos_in 43 i input pin for ldo1 (vpos) vpos 44 o positive supply output pin for panel source drivers vin3p3 45 i input pin to 3.3-v power switch v3p3 46 o output pin of 3.3-v power switch 4 submit documentation feedback copyright ? 2011, texas instruments incorporated product folder link(s): tps65185
tps65185 www.ti.com slvsaq8b C february 2011 C revised october 2011 terminal i/o description name no. thermistor input pin. connect a 10k ntc thermistor and a 43k linearization resistor ts 47 i between this pin and agnd. agnd2 48 reference point to external thermistor and linearization resistor power pad, internally connected to pbkg. connect to vn with short, wide trace. wide powerpad n/a copper trace will improve heat dissipation. powerpad must not be connected to ground. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) (2) value unit input voltage range at vin (2) , vin_p, vin3p3 C 0.3 to 7 v ground pins to system ground C 0.3 to 0.3 v voltage range at sda, scl, wakeup, pwrup, vcom_ctrl, vddh_fb, vee_fb, C 0.3 to 3.6 v pwr_good, nint voltage on vb, vb_sw, vpos_in, vpos_dis, vddh_in C 0.3 to 20 v vddh_dis C 0.3 to 30 v voltage on vn, vee_in, vcom_pwr, vneg_dis, vneg_in C 20 to 0.3 v voltage from vin_p to vn_sw C 0.3 to 30 v voltage on vcom_dis C 5 to 0.3 v vee_dis C 30 to 0.3 v peak output current internally limited ma continuous total power dissipation 2 w ja junction-to-ambient thermal resistance (3) 23 c/w t j operating junction temperature -10 to 125 c t a operating ambient temperature (4) -10 to 85 c t stg storage temperature -65 to 150 c (hbm) human body model 2000 esd rating v (cdm) charged device model 500 (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute maximum rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to network ground terminal. (3) estimated when mounted on high k jedec board per jesd 51-7 with thickness of 1.6 mm, 4 layers, size of 76.2 mm x 114.3 mm, and 2 oz. copper for top and bottom plane. actual thermal impedance will depend on pcb used in the application. (4) it is recommended that copper plane in proper size on board be in contact with die thermal pad to dissipate heat efficiently. thermal pad is electrically connected to pbkg, which is supposed to be tied to the output of buck-boost converter. thus wide copper trace in the buck-boost output will help heat dissipated efficiently. recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit input voltage range at vin, vin_p, vin3p3 3 3.7 6 v voltage range at sda, scl, wakeup, pwrup, vcom_ctrl, 0 3.6 v vddh_fb, vee_fb, pwr_good, nint t a operating ambient temperature range C 10 85 c t j operating junction temperature range C 10 125 c copyright ? 2011, texas instruments incorporated submit documentation feedback 5 product folder link(s): tps65185
tps65185 slvsaq8b C february 2011 C revised october 2011 www.ti.com recommended external components part number value size manufacturer inductors lqh44pn4r7mp0 4.7 h 4 mm x 4 mm x 1.65 mm murata nr4018t4r7m 4.7 h 4 mm x 4 mm x 1.8 mm taiyo yuden vls252015et-2r2m 2.2 h 2 mm x 2.5 mm x 1.5 mm tdk nr4012t2r2m 2.2 h 4 mm x 4 mm x 1.2 mm taiyo yuden capacitors grm21bc81e475ka12l 4.7 f, 25 v, x6s 805 murata grm32er71h475ka88l 4.7 f, 50 v, x7r 1210 murata all other caps x5r or better diodes bas3010 sod-323 infineon mbr130t1 sod-123 on-semi bav99 sot-23 fairchild thermistor ncp18xh103f03rb 10 k 603 murata electrical characteristics v in = 3.7 v, t a = C 10 c to 85 o c, typical values are at t a = 25 o c (unless otherwise noted) parameter test conditions min typ max unit input voltage v in input voltage range 3 3.7 6 v v uvlo undervoltage lockout threshold v in falling 2.9 v v hys undervoltage lockout hysteresis v in rising 400 mv input current i q operating quiescent current into v in device switching, no load 5.5 ma i std operating quiescent current into v in device in standby mode 130 a i sleep shutdown current device in sleep mode 3.5 10 a internal supplies vi nt_ldo internal supply 2.7 v c int_ldo nominal output capacitor capacitor tolerance 10% 1 4.7 f v ref internal supply 2.25 v c ref nominal output capacitor capacitor tolerance 10% 3.3 4.7 f dcdc1 (positive boost regulator) v in input voltage range 3 3.7 6 v power good threshold fraction of nominal output voltage 90 % pg power good time-out not tested in production 50 ms output voltage range 16 v v out dc set tolerance -4.5 4.5 % i out output current 250 ma r ds(on) mosfet on resistance v in = 3.7 v 350 m ? switch current limit 1.5 (1) a i limit switch current accuracy -30 30 % f sw switching frequency 1 mhz l dcdc1 inductor 2.2 h c dcdc1 nominal output capacitor capacitor tolerance 10% 1 2x4.7 f esr output capacitor esr 20 m ? (1) contact factory for 1-a, 2-a, or 2.5-a option. 6 submit documentation feedback copyright ? 2011, texas instruments incorporated product folder link(s): tps65185
tps65185 www.ti.com slvsaq8b C february 2011 C revised october 2011 electrical characteristics (continued) v in = 3.7 v, t a = C 10 c to 85 o c, typical values are at t a = 25 o c (unless otherwise noted) parameter test conditions min typ max unit dcdc2 (inverting buck-boost regulator) v in input voltage range 3 3.7 6 v power good threshold fraction of nominal output voltage 90 % pg power good time-out not tested in production 50 ms output voltage range -16 v v out dc set tolerance -4.5 4.5 % i out output current 250 ma r ds(on) mosfet on resistance v in = 3.7 v 350 m ? switch current limit 1.5 (2) a i limit switch current accuracy -30 30 % l dcdc1 inductor 4.7 h c dcdc1 nominal output capacitor capacitor tolerance 10% 1 3x4.7 f esr capacitor esr 20 m ? ldo1 (vpos) v pos_in input voltage range 15.2 16 16.8 v power good threshold fraction of nominal output voltage 90 % pg power good time-out not tested in production 50 ms v in = 16 v, v set output voltage set value 14.25 15 v vset[2:0] = 0x3h to 0x6h v interval output voltage set resolution v in = 16 v 250 mv v outtol output tolerance v set = 15 v, i load = 20 ma -1 1 % v dropout dropout voltage i load = 120 ma 250 mv v loadreg load regulation C dc i load = 10% to 90% 1 % i load load current range 120 ma i limit output current limit 120 ma discharge impedance to ground enabled when rail is disabled 800 1000 1200 r dis mismatch to any other rdis -2 2 % c ldo1 nominal output capacitor capacitor tolerance 10% 1 4.7 f ldo2 (vneg) v neg_in input voltage range 15.2 16 16.8 v power good threshold fraction of nominal output voltage 90 % pg power good time-out not tested in production 50 ms v in = C 16 v v set output voltage set value -15 -14.25 v vset[2:0] = 0x3h to 0x6h v interval output voltage set resolution v in = C 16 v 250 mv v outtol output tolerance v set = C 15 v, i load = C 20 ma -1 1 % v dropout dropout voltage i load = 120 ma 250 mv v loadreg load regulation C dc i load = 10% to 90% 1 % i load load current range 120 ma i limit output current limit 180 ma discharge impedance to ground enabled when rail is disabled 800 1000 1200 r dis mismatch to any other rdis -2 2 % t ss soft start time not tested in production 1 ms c ldo2 nominal output capacitor capacitor tolerance 10% 1 4.7 f (2) contact factory for 1-a, 2-a, or 2.5-a option. copyright ? 2011, texas instruments incorporated submit documentation feedback 7 product folder link(s): tps65185
tps65185 slvsaq8b C february 2011 C revised october 2011 www.ti.com electrical characteristics (continued) v in = 3.7 v, t a = C 10 c to 85 o c, typical values are at t a = 25 o c (unless otherwise noted) parameter test conditions min typ max unit ld01 (pos) and ldo2 (vneg) tracking v set = 15 v, v diff difference between vpos and vneg -50 50 mv i load = 20 ma, 0 c to 60 c vcom driver i vcom drive current 15 ma outside this range vcom is shut down allowed operating range -5.5 1 v and vcomf interrupt is set vcom[8:0] = 0x07dh -0.8 0.8 (-1.25 v), v in = 3.4 v to 4.2 v, no load accuracy % vcom[8:0] = 0x07dh v com -1.5 1.5 (-1.25 v), v in = 3.0 v to 6.0 v, no load output voltage range -5.11 0 v resolution 1lsb 10 mv max number of eeprom writes v com calibration 100 r in input impedance, hiz state hiz = 1 150 m discharge impedance to ground vcom_ctrl = low, hiz = 0 800 1000 1200 r dis mismatch to any other r dis -2 2 % c vcom nominal output capacitor capacitor tolerance 10% 3.3 4.7 f cp1 (vddh) charge pump v ddh_in input voltage range 15.2 16 16.8 v power good threshold fraction of nominal output voltage 90 % pg power good time-out not tested in production 50 ms feedback voltage 0.998 v v fb accuracy i load = 2 ma -2 2 % v ddh_out output voltage range v set = 22 v, i load = 2 ma 21 22 23 v i load load current range 10 ma f sw switching frequency 560 khz discharge impedance to ground enabled when rail is disabled 800 1000 1200 r dis mismatch to any other r dis -2 2 % c d driver capacitor 10 nf c o output capacitor 1 2.2 f cp2 (vee) negative charge pump v ee_in input voltage range 15.2 16 16.8 v power good threshold fraction of nominal output voltage 90 % pg power good time-out not tested in production 50 ms feedback voltage -0.994 v v fb accuracy i load = 2 ma -2 2 % v ee_out output voltage range v set = C 20 v, i load = 3 ma -21 -20 -19 v i load load current range 12 ma f sw switching frequency 560 khz discharge impedance to ground enabled when rail is disabled 800 1000 1200 r dis mismatch to any other r dis -2 2 % c d driver capacitor 10 nf c o nominal output capacitor capacitor tolerance 10% 1 2.2 f 8 submit documentation feedback copyright ? 2011, texas instruments incorporated product folder link(s): tps65185
tps65185 www.ti.com slvsaq8b C february 2011 C revised october 2011 electrical characteristics (continued) v in = 3.7 v, t a = C 10 c to 85 o c, typical values are at t a = 25 o c (unless otherwise noted) parameter test conditions min typ max unit thermistor monitor (3) a tms temperature to voltage ratio not tested in production -0.0161 v/ c offset tms offset temperature = 0 c 1.575 v v tms_hot temp hot trip voltage (t = 50 c) temp_hot_set = 0x8c 0.768 v v tms_cool temp hot escape voltage (t = 45 c) temp_cool_set = 0x82 0.845 v v tms_max maximum input level 2.25 v r ntc_pu internal pull up resistor 7.307 k r linear external linearization resistor 43 k adc res adc resolution not tested in production, 1 bit 16.1 mv adc del adc conversion time not tested in production 19 s tmst tol accuracy not tested in production -1 1 lsb logic levels and timing charteristics (scl, sda, pwr_good, pwrx, wakeup) i o = 3 ma, sink current v ol output low threshold level 0.4 v (sda, nint, pwr_good) v il input low threshold level 0.4 v v ih input high threshold level 1.2 v i (bias) input bias current v io = 1.8 v 1 a deglitch time, wakeup pin not tested in production 500 t deglitch s deglitch time, pwrup pin not tested in production 400 t discharge discharge delay not tested in production 100 (4) ms f scl scl clock frequency 400 khz i 2 c slave address 7-bit address 0x68h (5) oscillator f osc oscillator frequency 9 mhz frequency accuracy t a = C 40 c to 85 c -10 10 % thermal shutdown t shtdwn thermal trip point 150 c thermal hysteresis 20 c (3) 10-k murata ncp18xh103f03rb thermistor (1%) in parallel with a linearization resistor (43 k , 1%) are used at ts pin for panel temperature measurement. (4) contact factory for 50-ms, 200-ms or 400-ms option. (5) contact factory for alternate address of 0x48h. copyright ? 2011, texas instruments incorporated submit documentation feedback 9 product folder link(s): tps65185
tps65185 slvsaq8b C february 2011 C revised october 2011 www.ti.com typical characteristics default power-up sequence default power-down sequence figure 1. figure 2. inrush current @ v in = 3.7 v, c in = 100 f inrush current @ v in = 5 v, c in = 100 f figure 3. figure 4. switching wave forms, vn switching wave forms, vb v in = 3 v, r load, vpos = 330 , r load, vneg = 330 , v in = 3 v, r load, vpos = 330 , r load, vneg = 330 , no load on vddh, vee no load on vddh, vee figure 5. figure 6. 10 submit documentation feedback copyright ? 2011, texas instruments incorporated product folder link(s): tps65185
tps65185 www.ti.com slvsaq8b C february 2011 C revised october 2011 typical characteristics (continued) switching wave forms, vn switching wave forms, vb v in = 3.7 v, r load, vpos = 330 , r load, vneg = 330 , v in = 3.7 v, r load, vpos = 330 , r load, vneg = 330 , no load on vddh, vee no load on vddh, vee figure 7. figure 8. switching wave forms, vn switching wave forms, vb v in = 5 v, r load, vpos = 330 , r load, vneg = 330 , v in = 5 v, r load, vpos = 330 , r load, vneg = 330 , no load on vddh, vee no load on vddh, vee figure 9. figure 10. vn dcdc efficiency, t = 25 c vb dcdc efficiency, t = 25 c figure 11. figure 12. copyright ? 2011, texas instruments incorporated submit documentation feedback 11 product folder link(s): tps65185 0 10 20 30 40 50 60 70 80 90 100 0 25 50 75 100 125 150 175 output current [m a] efficiency [%] v in= 3. 5 v in= 5v 0 10 20 30 40 50 60 70 80 90 100 0 25 50 75 100 125 150 175 output current [m a] efficiency [%] vin= 3. 5 vin= 5v
tps65185 slvsaq8b C february 2011 C revised october 2011 www.ti.com typical characteristics (continued) vee charge pump efficiency, t = 25 c vddh charge pump efficiency, t = 25 c figure 13. figure 14. 3p3v switch impedance source driver supply tracking v in = 3.7 v, i load, v3p3 = 10 ma v in = 3.7 v figure 15. figure 16. vcom integrated non-linearity vcom differential non-linearity v in = 3.7 v, r load, vcom = 1 k v in = 3.7 v, r load, vcom = 1 k figure 17. figure 18. 12 submit documentation feedback copyright ? 2011, texas instruments incorporated product folder link(s): tps65185 0 10 20 30 40 50 60 70 80 90 100 0 2 4 6 8 10 12 output current [ma] efficiency [%] vin=5v vin=3.5v 0 10 20 30 40 50 60 70 80 90 100 0 2 4 6 8 10 12 output current [ma] efficiency [%] vin=5v vin=3. 5 -5 0 -4 0 -3 0 -2 0 -1 0 0 1 0 2 0 3 0 4 0 5 0 0 25 50 75 100 125 1 50 1 75 c u rre n t [m a] vpos + vneg[mv] ipo s = ine g ipo s s we ep, in e g= 15m a ipo s = 15m a , in eg s w eep 0 5 10 15 20 25 1 1.5 2 2.5 3 3.5 4 vin3p3[v] r[ ], (vin3p3-v3p3)/10ma w -5 -4 -3 -2 -1 0 1 2 3 4 5 0 64 128 192 25 6 320 384 44 8 512 vc o m c od e inl [mv] -0.2 -0 .15 -0.1 -0 .05 0 0 .05 0.1 0 .15 0.2 0 6 4 12 8 1 92 2 56 3 20 384 448 512 v co m c od e dnl[lsb]
tps65185 www.ti.com slvsaq8b C february 2011 C revised october 2011 typical characteristics (continued) kickback voltage measurement timing kickback voltage measurement error v in = 3.7 v; avg[1:0] = 00 (single measurement) v in = 3.7 v time from acq bit set to acqc interrupt received figure 19. figure 20. kickback voltage measurement timing v in = 3.7 v; avg[1:0] = 11 (eight measurements) time from acq bit set to acqc interrupt received figure 21. copyright ? 2011, texas instruments incorporated submit documentation feedback 13 product folder link(s): tps65185 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 0 640 12 80 192 0 2560 3200 3840 44 80 512 0 f o rce d kick ba c k vo lta g e [m v] measurementerror [lsb]
tps65185 slvsaq8b C february 2011 C revised october 2011 www.ti.com modes of operation the tps65185 has three modes of operation, sleep, standby, and active. sleep mode is the lowest-power mode in which all internal circuitry is turned off. in standby, all power rails are shut down but the device is ready to accept commands through the i 2 c interface. in active mode one or more power rails are enabled. sleep this is the lowest power mode of operation. all internal circuitry is turned off, registers are reset to default values and the device does not respond to i 2 c communications. tps65185 enters sleep mode whenever wakeup pin is pulled low. standby in standby all internal support circuitry is powered up and the device is ready to accept commands through the i 2 c interface but none of the power rails are enabled. the device enters standby mode when the wakeup pin is pulled high and either the pwrup pin is pulled low or the standby bit is set. the device also enters standby mode if input under voltage lock out (uvlo), positive boost under voltage (vb_uv), or inverting buck-boost under voltage (vn_uv) is detected, thermal shutdown occurs, or the prog bit is set (see vcom calibration). active the device is in active mode when any of the output rails are enabled and no fault condition is present. this is the normal mode of operation while the device is powered up. mode transisitons sleep active wakeup pin is pulled high with pwrup pin high. rails come up in the order defined by the upseqx registers (ok to tie wakeup and pwrup pin together). sleep standby wakeup pin is pulled high with pwrup pin low. rails will remain powered down. standby active wakeup pin is high and pwrrup pin is pulled high (rising edge) or the active bit is set. output rails will power up in the order defined by the upseqx registers. active standby wakeup pin is high and standby bit is set or pwrup pin is pulled low (falling edge). rails are shut down in the order defined by dwnseqx registers. device also enters standby in the event of thermal shut down (tsd), under voltage lock out (uvlo), positive boost or inverting buck-boost under voltage (uv), vcom fault (vcomf), or when the prog bit is set (see vcom calibration). standby sleep wakeup pin is pulled low while none of the output rails are enabled. active sleep wakeup pin is pulled low while at least one output rail is enabled. rails are shut down in the order defined by dwnseqx registers. 14 submit documentation feedback copyright ? 2011, texas instruments incorporated product folder link(s): tps65185
tps65185 www.ti.com slvsaq8b C february 2011 C revised october 2011 figure 22. global state diagram copyright ? 2011, texas instruments incorporated submit documentation feedback 15 product folder link(s): tps65185 sleep active rails = on i2c = yes power down wakeup = high & pwrup= low all rails = off v3p3 switch = off i2c = no registers default battery removed standby wakeup = high & (active bit = 1 || pwrup( ) ) all rails = off i2c = yes wakeup = high & (standby bit = 1|| pwrup( ? ) || fault ) wakeup = low wakeup = high & pwrup = high notes: ||, & = logic or, logic and. ( ), ( ? ) = rising edge, falling edge. uvlo = under voltage lock out tsd = thermal shut down uv = under voltage fault = uvlo || tsd || boost uv || vcom fault. wakeup = low ? ?
tps65185 slvsaq8b C february 2011 C revised october 2011 www.ti.com wake-up and power up sequencing the power-up/down order and timing is defined by user register settings. the default settings support the e ink ? vizplex ? panel and typically do not need to be changed. in sleep mode the tps65185 is completely turned off, the i 2 c registers are reset, and the device does not accept any i 2 c transaction. pull the wakeup pin high with the pwrup pin low and the device enters standby mode which enables the i 2 c interface. write to the upseq0 register to define the order in which the output rails are enabled at power-up and to the upseq1 registers to define the power-up delays between rails. finally, set the active bit in the enable register to 1 to execute the power-up sequence and bring up all power rails. alternatively pull the pwrup pin high (rising edge). after the active bit has been set, the negative boost converter (vn) is powered up first, followed by the positive boost (vb). the positive boost enable is gated by the internal power-good signal of the negative boost. once vb is in regulation, it issues an internal power-good signal and after delay time udly1 has expired, strobe1 is issued. the rail assigned to strobe1 will power up next and after its power-good signal has been asserted and delay time udly2 has expired, strobe2 is issued. the sequence continues until strobe4 has occurred and the last rail has been enabled. to power-down the device, set the standby bit of the enable register to 1 or pull the pwrup pin low (falling edge) and the tps65185 will power down in the order defined by dwnseqx registers. the delay times ddly2, ddly3, and ddly4 are weighted by a factor of dfctr which allows the user to space out the power-down of the rails to avoid crossing during discharge. dfctr is located in register dwnseq1. the positive boost (vb) is shut down together with the last rail at strobe4. however, the negative boost (vn) remains up and running for another 100 ms (discharge delay) to allow complete discharge of all rails. after the discharge delay, vn is powered down and the device enters standby or sleep mode, depending on the wakeup pin. if either the active bit is set or the pwrup pin is pulled high while the device is powering down, the power-down sequence (strobe1-4) is completed first, followed by a power-up sequence. vb and vn may or may not be powered down and the discharge delay may be cut short depending on the relative timing of strobe4 to the new power-up event. during power-up, if the standby bit is set or the pwrup pin is pulled low, the power-up sequence is aborted and the power-down sequence starts immediately. dependencies between rails charge pumps, ldos, and vcom driver are dependent on the positive and inverting buck-boost converters and several dependencies exist that affect the power-up sequencing. these dependencies are listed below. 1. inverting buck-boost (dcdc2) must be in regulation before positive boost (dcdc1) can be enabled. internally, dcdc1 enable is gated by dcdc2 power good. 2. positive boost (dcdc1) must be in regulation before ldo2 (vneg) can be enabled. internally ldo2 enable is gated dcdc1 power-good. 3. positive boost (dcdc1) must be in regulation before vcom can be enabled; internally vcom enable is gated by dcdc1 power good. 4. positive boost (dcdc1) must be in regulation before negative charge pump (cp2) can be enabled. internally cp2 enable is gated by dcdc1 power good. 5. positive boost (dcdc1) must be in regulation before positive charge pump (cp1) can be enabled. internally cp1 enable is gated by dcdc1 power good. 6. ldo2 must be in regulation before ldo1 can be enabled. internally ldo1 enable is gated by ldo2 power good. 16 submit documentation feedback copyright ? 2011, texas instruments incorporated product folder link(s): tps65185
tps65185 www.ti.com slvsaq8b C february 2011 C revised october 2011 top: power-up sequence is defined by assigning strobes to individual rails. strobe1 is the first strobe to occur after active bit is set and strobe4 is the last event in the sequence. strobes are assigned to rails in upseq0 register and delays between strobes are defined in upseq1 register. bottom: power-down sequence is independent of power-up sequence. strobes and delay times for power down sequence are set in dwnseq0 and dwnseq1 register. figure 23. power-up and power-down sequence copyright ? 2011, texas instruments incorporated submit documentation feedback 17 product folder link(s): tps65185 udly1 active bit or wakeup high vn pg vb pg udly2 pg1 strobe 1 strobe 2 udly3 pg2 strobe 3 udly4 pg3 strobe 4 pg4 standby bit or wakeup low strobe 2 strobe 1 ddly1 ddly2 ddly3 strobe 3 strobe 4 ddly4 discharge delay vb powers up 1 st rail powers up 2 nd rail powers up 3 nd rail powers up 4 th rail powers up 4 th rail powers down 3 nd rail powers down 2 nd rail powers down 1 st rail powers down vb powers down vn powers down vn powers up
tps65185 slvsaq8b C february 2011 C revised october 2011 www.ti.com in this example the first power-up sequence is started by pulling the pwrup pin high (rising edge). power-down is initiated by pulling the wakeup pin low (device enters sleep mode). the 2nd power-up sequence is initiated by pulling the wakeup pin high while the pwrup pin is also high (power up from sleep to active). figure 24. power-up and power-down timing diagram softstart tps65185 supports soft-start for all rails, i.e. inrush current is limited during startup of dcdc1, dcdc2, ldo1, ldo2, cp1 and cp2. if dcdc1 or dcdc2 are unable to reach power-good status within 50 ms, the corresponding uv flag is set in the interrupt registers, the interrupt pin is pulled low, and the device enters standby mode. ldo1, ldo2, positive and negative charge pumps also have a 50-ms power-good time-out limit. if either rail is unable to power up within 50 ms after it has been enabled, the corresponding uv flag is set and the interrupt pin is pulled low. however, the device will remain in active mode in this case. active discharge tps65185 provides low-impedance discharge paths for the display power rails (vee, vneg, vpos, vddh, and vcom) which are enabled whenever the corresponding rail is disabled. the discharge paths are connected to the rails on the pcb which allows adding external resistors to customize the discharge time. however, external resistors are not required. active discharge remains enabled for 100 ms after the last rail has been disabled (strobe4 has been executed). during this time the negative boost converter (vn) remains up. after the discharge delay, vn is shut down and the device enters standby or sleep mode, depending on the state of the wakeup pin. 18 submit documentation feedback copyright ? 2011, texas instruments incorporated product folder link(s): tps65185 vin pwrup wakeup vneg vee vpos vddh pwr_good vn vb 1.8ms (1) ddly 2 ddly 3 ddly 4 ddly 1 300 us (max) standby active sleep active (1) minimum delay time between wakeup rising edge and ic rady to accept i 2c transaction . udly 2 udly 3 udly 1 udly 4 i2c 300 us (max) udly 2 udly 1 udly 4 udly3 discharge delay
tps65185 www.ti.com slvsaq8b C february 2011 C revised october 2011 vpos/vneg supply tracking ldo1 (vpos) and ldo2 (vneg) track each other in a way that they are of opposite sign but same magnitude. the sum of vldo1 and vlod2 is guaranteed to be < 50 mv. v3p3 power switch the integrated power switch is used to cut the 3.3-v supply to the epd panel and is controlled through the v3p3_en pin of the enable register. in sleep mode the switch is automatically turned off and its output is discharged to ground. the default power-up state is off. to turn the switch on, set the v3p3_enbit to 1. vcom adjustment vcom is the output of a power-amplifier with an output voltage range of 0 v to -5.11 v, adjustable in 10-mv steps. in a typical application vcom is connected to the vcom terminal of the epd panel and the amplifier is controlled through the vcom_ctrl pin. with vcom_ctrl high, the amplifier drives the vcom pin to the voltage specified by the vcom1 and vcom2 register. when pulled low, the amplifier turns off and vcom is actively discharged to ground through vcom_dis pin. if active discharge is not desired, simply leave the vcom_dis pin open. for ease of design, the vcom_ctrl pin may also be tied to the battery or io supply. in this case, vcom is enabled with strobe4 during the power-up sequence and disabled on strobe1 of the power-down sequence. therefore vcom is the last rail to be enabled and the first to be disabled. kick-back voltage measurement tps65185 can perform a voltage measurement on the vcom pin to determine the kick-back voltage of the panel. this allows in-system calibration of vcom. to perform a kick-back voltage measurement, follow these steps: ? pull the wakeup pin and the pwrup pin high to enable all output rails. ? set the hiz bit in the vcom2 register. this puts the vcom pin in a high-impedance state. ? drive the panel with the null waveform. refer to e-ink specification for detail. ? set the acq bit in the vcom2 register to 1. this starts the measurement routine. ? when the measurement is complete, the acqc (acquisition complete) bit in the int1 register is set and the nint pin is pulled low. ? the measurement result is stored in the vcom[8:0] bits of the vcom1 and vcom2 register. please note that the measurement result is not automatically programmed into non-volatile memory. changing the power-up default is described in the following paragraph. storing the vcom power-up default value in memory the power-up default value of vcom can be user-set and programmed into non-volatile memory. to do so, write the default value to the vcom[8:0] bits of the vcom1 and vcom2 register, then set the prog bit in vcom2 register to 1. first, all power rails are shut-down, then the vcom[8:0] value is committed to non-volatile memory such that it becomes the new power-up default. once programming is complete, the prgc bit in the int1 register is set and the nint pin is pulled low. to verify that the new value has been saved properly, first write the vcom[8:0] bits to 0x000h, then pull the wakeup pin low. after the wakeup pin is pulled back high, read the vcom[8:0] bits to verify that the new default value is correct. copyright ? 2011, texas instruments incorporated submit documentation feedback 19 product folder link(s): tps65185
tps65185 slvsaq8b C february 2011 C revised october 2011 www.ti.com figure 25. block diagram of vcom circuit 20 submit documentation feedback copyright ? 2011, texas instruments incorporated product folder link(s): tps65185 vin 10uf vcom_pwr 4.7uf to panel back -plane (-0.5 to -5.0v, 15ma) from input supply (3.0v-6.0v) 4.7uf vref agnd1 dac vcom vcom[8:0] vcom_ctrl vcom_dis 4.7uf from uc 500 vref from vn (-17v) 4.7uf int_ldo int_ldo
tps65185 www.ti.com slvsaq8b C february 2011 C revised october 2011 figure 26. vcom calibration flow copyright ? 2011, texas instruments incorporated submit documentation feedback 21 product folder link(s): tps65185 pull wakeup = high pull pwrup= high write hiz = 1 device enters active mode all power rails are up except vcom vcom pin is in hiz state processor drives panel with null waveform write acq = 1 starts a/d conversion wait for acqc interrupt indicates a/d conversion is complete if avg[1:0] is <> 00, interrupt is issed after all conversions are complete and average has been calcutated. read result from vcom1/2 registers pull pwrup= low write hiz = 0 check result and decide to keep the value or repeat measurment. device enters standby mode write prog= 1 starts the eeprom programming cycle. power must not be interrupted. wait for prgc interrupt indicates programming is complete pull wakeup = low device enters sleep mode pull wakeup = high device enters standby mode read vcom[8:0] compare against written value toconfirm new default has been programmed correctly. setup measurement programming verification
tps65185 slvsaq8b C february 2011 C revised october 2011 www.ti.com fault handling and recovery the tps65185 monitors input and output voltages and die temperature and will take action if operating conditions are outside normal limits. whenever the tps65185 encounters: ? thermal shutdown (tsd) ? positive boost under voltage (vb_uv) ? inverting buck-boost under voltage (vn_uv) ? input under voltage lock out (uvlo) it shuts down all power rails and enters standby mode. shut-down follows the order defined by dwnseqx registers. the exception is vcom fault witch leads to immediate shutdown of all rails. once a fault is detected, the pwr_good and nint pins are pulled low and the corresponding interrupt bit is set in the interrupt register. power rails cannot be re-enabled unless the interrupt bits have been cleared by reading the int1 and int2 register. alternatively, toggling the wakeup pin also resets the interrupt bits. as the pwrup input is edge sensitive, the host must toggle the pwrup pin to re-enable the rails through gpio control, i.e. it must bring the pwrup pin low before asserting it again. alternatively rails can be re-enbled through the i 2 c interface. whenever the tps65185 encounters under-voltage on vneg (vneg_uv), vpos (vpos_uv), vee (vee_uv) or vddh (vddh_uv), rails are not shut down but the pwr_good and nint is pulled low with the corresponding interrupt bit set. the device remains in active mode and recovers automatically once the fault has been removed. power good pin the power good pin (pwr_good) is an open drain output that is pulled high (by an external pull-up resistor) when all four power rails (cp1, cp2, ldo1, ldo2) are in regulation and is pulled low if any of the rails encounters a fault or is disabled. pwr_good remains low if one of the rails is not enabled by the host and only after all rails are in regulation pwr_good is released to hiz state (pulled up by external resistor). interrupt pin the interrupt pin (nint) is an open drain output that is pulled low whenever one or more of the int1 or int2 bits are set. the nint pin is released (returns to hiz state) and fault bits are cleared once the register with the set bit has been read by the host. if the fault persists, the nint pin will be pulled low again after a maximum of 32 s. interrupt events can be masked by re-setting the corresponding enable bit in the int_en1 and int_en2 register, i.e. the user can determine which events cause the nint pin to be pulled low. the status of the enable bits affects the nint pin only and has no effect on any of the protection and monitoring circuits or the int1/int2 bits themselves. note that persisting faults such as thermal shutdown can cause the nint pin to be pulled low for an extended period of time which can keep the host in a loop trying to resolve the interrupt. if this behavior is not desired, set the corresponding mask bit after receiving the interrupt and keep polling the int1/int2 register to see when the fault condition has disappeared. after the fault is resolved, unmask the interrupt bit again. panel temperature monitoring the tps65185 provides circuitry to bias and measure an external negative temperature coefficient resistor (ntc) to monitor the display panel temperature in a range from -10 c to 85 c with and accuracy of 1 c from 0 c to 50 c. temperature measurement must be triggered by the controlling host and the last temperature reading is always stored in the tmst_value register. interrupts are issued when the temperature exceeds the programmable hot, or drops below the programmable cold threshold, or when the temperature has changed by more than a user-defined threshold from the baseline value. details are explained under hot, cold, and temperature-change interrupts . 22 submit documentation feedback copyright ? 2011, texas instruments incorporated product folder link(s): tps65185
tps65185 www.ti.com slvsaq8b C february 2011 C revised october 2011 ntc bias circuit figure 27 below shows the block diagram of the ntc bias and measurement circuit. the ntc is biased from an internally generated 2.25-v reference voltage through an integrated 7.307-k bias resistor. a 43-k resistor is connected parallel to the ntc to linearize the temperature response curve. the circuit is designed to work with a nominal 10-k ntc and achieves accuracy of 1 c from 0 c to 50 c. the voltage drop across the ntc is digitized by a 10-bit sar adc and translated into an 8-bit two s complement by digital per table 1 . table 1. adc output value vs termperature temperature tmst_value[7:0] < -10 c 1111 0110 -10 c 1111 0110 -9 c 1111 0111 ... ... -2 c 1111 1110 -1 c 1111 1111 0 c 0000 0000 1 c 0000 0001 2 c 0000 0010 ... ... 25 c 0001 1001 ... 85 c 0101 0101 > 85 c 0101 0101 figure 27. ntc bias and measurement circuit a temperature measurement is triggered by setting the read_therm bit of the tmst1 register to 1.during the a/d conversion the conv_end bit of the tmst1 register reads 0 , otherwise it reads 1 . at the end of the a/d conversion the eoc bit in the int2 register is set and the temperature value is available in the tmst_value register. hot, cold, and temperature-change interrupts each temperature acquisition is compared against the programmable tmst_hot and tmst_cold thresholds and to the baseline temperature, to determine if the display is within allowed operating temperature range and if the temperature has changed by more than a user-defined threshold since the last update. the first temperature reading after the wakeup pin has been pulled high automatically becomes the baseline temperature. any subsequent reading is compared against the baseline temperature. if the difference is equal or greater than the threshold value, an interrupt is issued (dtx bit in register int1 is set to 1 ) and the latest value becomes the new baseline. if the difference is less than the threshold value, no action is taken. the threshold value is defined by dt[1:0] bits in the tmst1 register and has a default value of 2 c. in summary: ? when the temperature is equal or less than the tmst_cold[3:0] threshold, the tmst_cold interrupt bit of the int1 register is set, and the nint pin is pulled low. ? when the temperature is greater than tmst_cold but lower then tmst_hot, no action is taken. copyright ? 2011, texas instruments incorporated submit documentation feedback 23 product folder link(s): tps65185 7.307k 2.25v 43k 10k ntc 10 adc digital ts agnd2
tps65185 slvsaq8b C february 2011 C revised october 2011 www.ti.com ? when the temperature is equal or greater than the tmst_hot[3:0] threshold, the tmst_hot interrupt bit of the int1 register is set, and the nint pin is pulled low. ? if the last temperature is different from the baseline temperature by 2 c (default) or more, the dtx interrupt bit of the int1 register is set. the latest temperature becomes the new baseline temperature. please note that by default the dtx interrupt is disabled, i.e. the nint pin is not pulled low unless the dtx_en bit was previously set high. ? if the last temperature change is less than 2 c (default), no action is taken. typical application of the temperature monitor in a typical application the temperature monitor and interrupts are used in the following manner: ? after the wakeup pin has been pulled high, the application processor (ap) writes 0x80h to the tmst1 register (address 0x0dh). this starts the temperature measurement. ? the ap waits for the eoc interrupt. alternatively the ap can poll the conv_end bit in register tmst1. this will notify the ap that the a/d conversion is complete and the new temperature reading is available in the tmst_value register (address (0x00h). ? the ap reads the temperature value from the tmst_value register (address (0x00h). ? if the temperature changes by 2 c (default) or more from the first reading, the processor is notified by the dtx interrupt. the a/p may or may not decide to select a different set of wave forms to drive the panel. ? if the temperature is outside the allowed operating range of the panel, the processor is notified by the thot and tcold interrupts, respectively. it may or may not decide to continue with the page update. ? once an over/under temperature has been detected, the ap should reset the tmst_hot_en or tmst_cold_en bits, respectively, to avoid the nint pin to be continuously pulled low. the tmst_hot and tmst_cold interrupt bits then should be polled continuously, to determine when the panel temperature recovers to the normal operating range. once the temperature has recovered, the tmst_hot_en or tmst_cold_en bits should be set to 1 again and normal operation can resume. i 2 c bus operation the tps65185 hosts a slave i 2 c interface that supports data rates up to 400 kbit/s and auto-increment addressing and is compliant to i 2 c standard 3.0. figure 28. subaddress in i 2 c transmission the i 2 c bus is a communications link between a controller and a series of slave terminals. the link is established using a two-wire bus consisting of a serial clock signal (scl) and a serial data signal (sda). the serial clock is sourced from the controller in all cases where the serial data line is bi-directional for data communication between the controller and the slave terminals. each device has an open drain output to transmit data on the serial data line. an external pull-up resistor must be placed on the serial data line to pull the drain output high during data transmission. data transmission is initiated with a start bit from the controller as shown in figure 30 . the start condition is recognized when the sda line transitions from high to low during the high portion of the scl signal. upon reception of a start bit, the device will receive serial data on the sda input and check for valid address and control information. if the appropriate slave address bits are set for the device, then the device will issue an acknowledge pulse and prepare to receive the register address. depending on the r/nw bit, the next byte received from the master is written to the addressed register (r/nw = 0) or the device responds with 8-bit data from the register (r/nw = 1). data transmission is completed by either the reception of a stop condition or the 24 submit documentation feedback copyright ? 2011, texas instruments incorporated product folder link(s): tps65185 s a6 a5 a4 a3 a2 a1 a0 a s7 s6 s5 s4 s3 s2 s1 s0 a d7 d6 d5 d4 d3 d2 d1 d0 a p s a start condition acknowledge a6 a0 ... device address r/nw read / not write s7 s0 ... sub-address d7 d0 ... data p stop condition r/nw slave address + r/nw reg address data
tps65185 www.ti.com slvsaq8b C february 2011 C revised october 2011 reception of the data word sent to the device. a stop condition is recognized as a low to high transition of the sda input during the high portion of the scl signal. all other transitions of the sda line must occur during the low portion of the scl signal. an acknowledge is issued after the reception of valid address, sub-address and data words. the i 2 c interfaces will auto-sequence through register addresses, so that multiple data words can be sent for a given i 2 c transmission. reference figure 29 and figure 30 for deail. top: master writes data to slave. bottom: master reads data from slave. figure 29. i 2 c data protocol figure 30. i 2 c start/stop/acknowledge protocol figure 31. i 2 c data transmission timing copyright ? 2011, texas instruments incorporated submit documentation feedback 25 product folder link(s): tps65185 s 1-7 8 9 1-7 8 9 1-7 8 9 p address r/w ack data ack data ack/ nack stop start sda scl t f t hd;sta t low t r t hd;dat t su;dat t high t su;sta t hd;sta t sp t su;sto t r t buf t f s s r s p sda scl slave address w a reg address a slave address r a data regaddr a s data regaddr +n a data regaddr + n+1 p from master to slavefrom slave to master s w a p start write (low) acknowlege stop r read (high) s not acknowlege n bytes + ack slave address w a reg address a data regaddr a s data subaddr +n a data subaddr +n+1 p n bytes + ack
tps65185 slvsaq8b C february 2011 C revised october 2011 www.ti.com data transmission timing v bat = 3.6 v 5%, t a = 25 o c, c l = 100 pf (unless otherwise noted) parameter test conditions min typ max unit f (scl) serial clock frequency 100 400 khz scl = 100 khz 4 s hold time (repeated) start condition. after this t hd;sta period, the first clock pulse is generated. scl = 400 khz 600 ns scl = 100 khz 4.7 t low low period of the scl clock s scl = 400 khz 1.3 scl = 100 khz 4 s t high high period of the scl clock scl = 400 khz 600 ns scl = 100 khz 4.7 s t su;sta set-up time for a repeated start condition scl = 400 khz 600 ns scl = 100 khz 0 3.45 s t hd;dat data hold time scl = 400 khz 0 900 ns scl = 100 khz 250 t su;dat data set-up time ns scl = 400 khz 100 scl = 100 khz 1000 t r rise time of both sda and scl signals ns scl = 400 khz 300 scl = 100 khz 300 t f fall time of both sda and scl signals ns scl = 400 khz 300 scl = 100 khz 4 s t su;sto set-up time for stop condition scl = 400 khz 600 ns scl = 100 khz 4.7 t buf bus free time between stop and start condition s scl = 400 khz 1.3 scl = 100 khz n/a n/a pulse width of spikes which mst be suppressed t sp ns by the input filter scl = 400 khz 0 50 scl = 100 khz 400 c b capacitive load for each bus line pf scl = 400 khz 400 26 submit documentation feedback copyright ? 2011, texas instruments incorporated product folder link(s): tps65185
tps65185 www.ti.com slvsaq8b C february 2011 C revised october 2011 register address map default register address (hex) name description value 0 0x00 tmst_value n/a thermistor value read by adc 1 0x01 enable n/a enable/disable bits for regulators 2 0x02 vadj n/a vpos/vneg voltage adjustment 3 0x03 vcom1 n/a voltage settings for vcom 4 0x04 vcom2 n/a voltage settings for vcom + control 5 0x05 int_en1 n/a interrupt enable group1 6 0x06 int_en2 n/a interrupt enable group2 7 0x07 int1 n/a interrupt group1 8 0x08 int2 n/a interrupt group2 9 0x09 upseq0 n/a power-up strobe assignment 10 0x0a upseq1 n/a power-up sequence delay times 11 0x0b dwnseq0 n/a power-down strobe assignment 12 0x0c dwnseq1 n/a power-down sequence delay times 13 0x0d tmst1 n/a thermistor configuration 14 0x0e tmst2 n/a thermistor hot temp set 15 0x0f pg n/a power good status each rails 16 0x10 revid n/a device revision id information thermistor readout (tmst_value) address C 0x00h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name tmst_value[7:0] read/write r r r r r r r r reset value n/a n/a n/a n/a n/a n/a n/a n/a field name bit definition temperature read-out 1111 0110 C < -10 c 1111 0110 C -10 c 1111 0111 C -9 c ... 1111 1110 C -2 c 1111 1111 C -1 c tmst_value[7:0] 0000 0000 C 0 c 0000 0001 C 1 c 0000 0010 C 2 c ... 0001 1001 C 25 c ... 0101 0101 C 85 c 0101 0101 C > 85 c copyright ? 2011, texas instruments incorporated submit documentation feedback 27 product folder link(s): tps65185
tps65185 slvsaq8b C february 2011 C revised october 2011 www.ti.com enable (enable) address C 0x01h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name active standby v3p3_en vcom_en vddh_en vpos_en vee_en vneg_en read/write r/w r/w r/w r/w r/w r/w r/w r/w reset value 0 0 0 0 0 0 0 0 field name bit definition (1) standby to active transition bit 1 C transition from standby to active mode. rails power up as defined by upseqx registers active 0 C no effect note: after transition bit is cleared automatically standby to active transition bit 1 C transition from standby to active mode. rails power up as defined by dwnseqx registers standby 0 C no effect note: after transition bit is cleared automatically. standby bit has priority over avtive. vin3p3 to v3p3 switch enable v3p3_en 1 C switch is on 0 C switch is off vcom buffer enable vcom_en 1 C enabled 0 C disabled vddh charge pump enable vddh_en 1 C enabled 0 C disabled vpos ldo regulator enable 1 C enabled vpos_en 0 C disabled note: vpos cannot be enabled before vneg is enabled. vee charge pump enable vee_en 1 C enabled 0 C disabled vneg ldo regulator enable 1 C enabled vneg_en 0 C disabled note: when vneg is disabled vpos will also be disabled. (1) enable bits always reflect actual status of the corresponding rail. 28 submit documentation feedback copyright ? 2011, texas instruments incorporated product folder link(s): tps65185
tps65185 www.ti.com slvsaq8b C february 2011 C revised october 2011 voltage adjustment register (vadj) address C 0x02h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name not used not used not used not used not used vset[2:0] read/write r/w r/w r/w r/w r r/w r/w r/w reset value 0 0 1 0 0 0 e2 1 e2 1 e2 field name bit definition not used n/a not used n/a not used n/a not used n/a not used n/a vpos and vneg voltage setting 000 - not valid 001 - not valid 010 - not valid vset[2:0] 011 - 15.000 v 100 - 14.750 v 101 - 14.500 v 110 - 14.250 v 111 - reserved vcom 1 (vcom1) address C 0x03h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name vcom [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w reset value 0 e2 1 e2 1 e2 1 e2 1 1 0 1 field name bit definition vcom[7:0] vcom voltage, least significant byte. see vcom2 register for details. copyright ? 2011, texas instruments incorporated submit documentation feedback 29 product folder link(s): tps65185
tps65185 slvsaq8b C february 2011 C revised october 2011 www.ti.com vcom 2 (vcom2) address C 0x04h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name acq prog hiz avg[1:0] not used not used vcom[8] read/write r/w r/w r/w r/w r/w r/w r/w r/w reset value 0 0 0 0 0 1 0 0 e2 field name bit definition kick-back voltage acquisition bit 1 C starts kick-back voltage measurement routine acq 0 C no effect note: after measurement is complete bit is cleared automatically and measurement result is reflected in vcom[8:0] bits. vcom programming bit 1 C vcom[8:0] value is committed to non-volatile memory and becomes new power-up default prog 0 C no effect note: after programming bit is cleared automatically and tps65185 will enter standby mode. vcom hiz bit hiz 1 C vcom pin is placed into hi-impedance state to allow vcom measurement 0 C vcom amplifier is connected to vcom pin number of acquisitions that is averaged to a single kick-back voltage measurement 00 C 1x 01 C 2x avg[1:0] 10 C 4x 11 C 8x note: when the acq bit is set, the state machine repeat the a/d conversion of the kick-back voltage avd[1:0] times and returns a single, averaged, value to vcom[8:0] not used n/a not used n/a vcom voltage adjustment vcom = vcom[8:0] x -10 mv in the range from 0 mv to -5.110 v 0x000h C 0 0000 0000 C -0 mv 0x001h C 0 0000 0001 C -10 mv 0x002h C 0 0000 0010 C -20 mv vcom[8:0] ... 0x07dh - 0 0111 1101 - -1250 mv ... 0x1feh C 1 1111 1110 C -5100 mv 0x1ffh C 1 1111 1111 C -5110 mv 30 submit documentation feedback copyright ? 2011, texas instruments incorporated product folder link(s): tps65185
tps65185 www.ti.com slvsaq8b C february 2011 C revised october 2011 interrupt enable 1 (int_en1) address C 0x05h data bit d7 d6 d5 d4 d3 d2 d1 d0 tmst_hot tmst_cold field name dtx_en tsd_en hot_en uvlo_en acqc_en prgc_en _en _en read/write r r/w r/w r/w r/w r/w r r reset value 0 1 1 1 1 1 1 1 field name bit definition (1) panel temperature-change interrupt enable dtx_en 1 C enabled 0 C disabled thermal shutdown interrupt enable tsd_en 1 C enabled 0 C disabled thermal shutdown early warning enable hot_en 1 C enabled 0 C disabled thermistor hot interrupt enable tmst_hot_en 1 C enabled 0 C disabled thermistor cold interrupt enable tmst_cold_en 1 C enabled 0 C disabled vin under voltage detect interrupt enable uvlo_en 1 C enabled 0 C disabled vcom acquisition complete interrupt enable acqc_en 1 C enabled 0 C disabled vcom programming complete interrupt enable prgc_en 1 C enabled 0 C disabled (1) enabled means nint pin is pulled low when interrupt occurs. disabled means nint pin is not pulled low when interrupt occurs. copyright ? 2011, texas instruments incorporated submit documentation feedback 31 product folder link(s): tps65185
tps65185 slvsaq8b C february 2011 C revised october 2011 www.ti.com interrupt enable 2 (int_en2) address C 0x06h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name vbuven vddhuven vnuv_en vposuven veeuven vcomfen vneguven eocen read/write r/w r/w r/w r/w r/w r/w r/w r/w reset value 1 1 1 1 1 1 1 1 field name bit definition (1) positive boost converter under voltage detect interrupt enable vbuven 1 C enabled 0 C disabled vddh under voltage detect interrupt enable vddhuven 1 C enabled 0 C disabled inverting buck-boost converter under voltage detect interrupt enable vnuven 1 C enabled 0 C disabled vpos under voltage detect interrupt enable vposuven 1 C enabled 0 C disabled vee under voltage detect interrupt enable veeuven 1 C enabled 0 C disabled vcom fault interrupt enable vcomfen 1 C enabled 0 C disabled vneg under voltage detect interrupt enable vneguven 1 C enabled 0 C disabled temperature adc end of conversion interrupt enable eocen 1 C enabled 0 C disabled (1) enabled means nint pin is pulled low when interrupt occurs. disabled means nint pin is not pulled low when interrupt occurs. 32 submit documentation feedback copyright ? 2011, texas instruments incorporated product folder link(s): tps65185
tps65185 www.ti.com slvsaq8b C february 2011 C revised october 2011 interrupt 1 (int1) address C 0x07h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name dtx tsd hot tmst_hot tmst_cold uvlo acqc prgc read/write r r r r r r r r reset value 0 n/a n/a n/a n/a n/a 0 0 field name bit definition panel temperature-change interrupt dtx 1 C temperature has changed by 3 deg or more over previous reading 0 C no significance thermal shutdown interrupt tsd 1 C chip is in over-temperature shutdown 0 C no fault thermal shutdown early warning hot 1 C chip is approaching over-temperature shutdown 0 C no fault thermistor hot interrupt tmst_hot 1 C thermistor temperature is equal or greater than tmst_hot threshold 0 C no fault thermistor cold interrupt tmst_cold 1 C thermistor temperature is equal or less than tmst_cold threshold 0 C no fault vin under voltage detect interrupt uvlo 1 C input voltage is below uvlo threshold 0 C no fault vcom acquisition complete acqc 1 C vcom measurement is compete 0 C no significance vcom programming complete prgc 1 C vcom programming is complete 0 C no significance copyright ? 2011, texas instruments incorporated submit documentation feedback 33 product folder link(s): tps65185
tps65185 slvsaq8b C february 2011 C revised october 2011 www.ti.com interrupt 2 (int2) address C 0x08h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name vb_uv vddh_uv vn_uv vpos_uv vee_uv vcomf vneg_uv eoc read/write r r r r r r r r reset value n/a n/a n/a n/a n/a n/a n/a n/a field name bit definition positive boost converter under voltage detect interrupt vb_uv 1 C under-voltage on dcdc1 detected 0 C no fault vddh under voltage detect interrupt vddh_uv 1 C under-voltage on vddh charge pump detected 0 C no fault inverting buck-boost converter under voltage detect interrupt vn_uv 1 C under-voltage on dcdc2 detected 0 C no fault vpos under voltage detect interrupt vpos_uv 1 C under-voltage on ldo1(vpos) detected 0 C no fault vee under voltage detect interrupt vee_uv 1 C under-voltage on vee charge pump detected 0 C no fault vcom fault detection vcomf 1 C fault on vcom detected (vcom is outside normal operating range) 0 C no fault vneg under voltage detect interrupt vneg_uv 1 C under-voltage on ldo2(vneg) detected 0 C no fault adc end of conversion interrupt eoc 1 C adc conversion is complete (temperature acquisition is complete) 0 C no significance 34 submit documentation feedback copyright ? 2011, texas instruments incorporated product folder link(s): tps65185
tps65185 www.ti.com slvsaq8b C february 2011 C revised october 2011 power up sequence register 0 (upseq0) address C 0x09h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name vddh_up[1:0] vpos_up[1:0] vee_up[1:0] vneg_up[1:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w reset value 1 e2 1 e2 1 e2 0 e2 0 e2 1 e2 0 e2 0 e2 field name bit definition vddh power-up order 00 C power up on strobe1 vddh_up[1:0] 01 C power up on strobe2 10 C power up on strobe3 11 C power up on strobe4 vpos power-up order 00 C power up on strobe1 vpos_up[1:0] 01 C power up on strobe2 10 C power up on strobe3 11 C power up on strobe4 vee power-up order 00 C power up on strobe1 vee_up[1:0] 01 C power up on strobe2 10 C power up on strobe3 11 C power up on strobe4 vneg power-up order 00 C power up on strobe1 vneg_up[1:0] 01 C power up on strobe2 10 C power up on strobe3 11 C power up on strobe4 figure 32. default power-up/down sequence copyright ? 2011, texas instruments incorporated submit documentation feedback 35 product folder link(s): tps65185 vneg vee vpos vddh 6ms 6ms 48ms 6ms 6ms 6ms
tps65185 slvsaq8b C february 2011 C revised october 2011 www.ti.com power up sequence register 1 (upseq1) address C 0x0ah data bit d7 d6 d5 d4 d3 d2 d1 d0 field name udly4[1:0] udly3[1:0] udly2[1:0] udly1[1:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w reset value 0 e2 1 e2 0 e2 1 e2 0 e2 1 e2 0 e2 1 e2 field name bit definition dly4 delay time set; defines the delay time from strobe3 to strobe4 during power-up. 00 C 3 ms udly4[1:0] 01 C 6 ms 10 C 9 ms 11 C 12 ms dly3 delay time set; defines the delay time from strobe2 to strobe3 during power-up. 00 C 3 ms udly3[1:0] 01 C 6 ms 10 C 9 ms 11 C 12 ms dly2 delay time set; defines the delay time from strobe1 to strobe2 during power-up. 00 C 3 ms udly2[1:0] 01 C 6 ms 10 C 9 ms 11 C 12 ms dly1 delay time set; defines the delay time from vn_pg high to strobe1 during power-up. 00 C 3 ms udly1[1:0] 01 C 6 ms 10 C 9 ms 11 C 12 ms 36 submit documentation feedback copyright ? 2011, texas instruments incorporated product folder link(s): tps65185
tps65185 www.ti.com slvsaq8b C february 2011 C revised october 2011 power down sequence register 0 (dwnseq0) address C 0x0bh data bit d7 d6 d5 d4 d3 d2 d1 d0 field name vddh_dwn[1:0] vpos_dwn[1:0] vee_dwn[1:0] vneg_dwn[1:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w reset value 0 e2 0 e2 0 e2 1 e2 1 e2 1 e2 1 e2 0 e2 field name bit definition vddh power-down order 00 C power down on strobe1 vddh_dwn[1:0] 01 C power down on strobe2 10 C power down on strobe3 11 C power down on strobe4 vpos power-down order 00 C power down on strobe1 vpos_dwn[1:0] 01 C power down on strobe2 10 C power down on strobe3 11 C power down on strobe4 vee power-down order 00 C power down on strobe1 vee_dwn[1:0] 01 C power down on strobe2 10 C power down on strobe3 11 C power down on strobe4 vneg power-down order 00 C power down on strobe1 vneg_dwn[1:0] 01 C power down on strobe2 10 C power down on strobe3 11 C power down on strobe4 copyright ? 2011, texas instruments incorporated submit documentation feedback 37 product folder link(s): tps65185
tps65185 slvsaq8b C february 2011 C revised october 2011 www.ti.com power down sequence register 1 (dwnseq1) address C 0x0ch data bit d7 d6 d5 d4 d3 d2 d1 d0 field name ddly4[1:0] ddly3[1:0] ddly2[1:0] ddly1 dfctr read/write r/w r/w r/w r/w r/w r/w r/w r/w reset value 1 e2 1 e2 1 e2 0 e2 0 e2 0 e2 0 e2 0 e2 field name bit definition dly4 delay time set; defines the delay time from strobe3 to strobe4 during power-down. 00 C 6 ms ddly4[1:0] 01 C 12 ms 10 C 24 ms 11 C 48 ms dly3 delay time set; defines the delay time from strobe2 to strobe3 during power-down. 00 C 6 ms ddly3[1:0] 01 C 12 ms 10 C 24 ms 11 C 4 8ms dly2 delay time set; defines the delay time from strobe1 to strobe2 during power-down. 00 C 6 ms ddly2[1:0] 01 C 12 ms 10 C 24 ms 11 C 48 ms dly2 delay time set; defines the delay time from wakeup low to strobe1 during power-down. ddly1 0 C 3 ms 1 C 6 ms at power-down delay time dly2[1:0], dly3[1:0], dly4[1:0] are multiplied with dfctr[1:0] dfctr 0 C 1x 1 C 16x 38 submit documentation feedback copyright ? 2011, texas instruments incorporated product folder link(s): tps65185
tps65185 www.ti.com slvsaq8b C february 2011 C revised october 2011 thermistor register 1 (tmst1) address C 0x0dh data bit d7 d6 d5 d4 d3 d2 d1 d0 field name read_therm not used conv_end not used not used not used dt[1:0] read/write r/w r/w r r/w r/w r/w r/w r/w reset value 0 0 1 0 0 0 0 0 field name bit definition read thermistor value 1 C initiates temperature acquisition read_therm 0 C no effect note: bit is self-cleared after acquisition is completed not used n/a adc conversion done flag conv_end 1 C conversion is finished 0 C conversion is not finished not used n/a not used n/a panel temperature-change interrupt threshold 00 C 2 c 01 C 3 c 10 C 4 c dt[1:0] 11 C 5 c dtx interrupt is issued when difference between most recent temperature reading and baseline temperature is equal to or greater than threshold value. see hot, cold, and temperature-change interrupts section for details. copyright ? 2011, texas instruments incorporated submit documentation feedback 39 product folder link(s): tps65185
tps65185 slvsaq8b C february 2011 C revised october 2011 www.ti.com thermistor register 2 (tmst2) address C 0x0eh data bit d7 d6 d5 d4 d3 d2 d1 d0 field name tmst_cold[3:0] tmst_hot[3:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w reset value 0 1 1 1 1 0 0 0 field name bit definition thermistor cold threshold 0000 C -7 c 0001 C -6 c 0010 C -5 c 0011 C -4 c 0100 C -3 c 0101 C -2 c 0110 C -1 c 0111 C 0 c tmst_cold [3:0] 1000 C 1 c 1001 C 2 c 1010 C 3 c 1011 C 4 c 1100 C 5 c 1101 C 6 c 1110 C 7 c 1111 C 8 c note: an interrupt is issued when thermistor temperature is equal or less than cold threshold thermistor hot threshold 0000 C 42 c 0001 C 43 c 0010 C 44 c 0011 C 45 c 0100 C 46 c 0101 C 47 c 0110 C 48 c 0111 C 49 c tmst_hot [3:0] 1000 C 50 c 1001 C 51 c 1010 C 52 c 1011 C 53 c 1100 C 54 c 1101 C 55 c 1110 C 56 c 1111 C 57 c note: an interrupt is issued when thermistor temperature is equal or greater than hot threshold 40 submit documentation feedback copyright ? 2011, texas instruments incorporated product folder link(s): tps65185
tps65185 www.ti.com slvsaq8b C february 2011 C revised october 2011 power good status (pg) address C 0x0fh data bit d7 d6 d5 d4 d3 d2 d1 d0 field name vb_pg vddh_pg vn_pg vpos_pg vee_pg not used vneg_pg not used read/write r r r r r r r r reset value 0 0 0 0 0 0 0 0 field name bit definition (1) positive boost converter power good vb_pg 1 C dcdc1 is in regulation 0 C dcdc1 is not in regulation or turned off vddh power good vddh_pg 1 C vddh charge pump is in regulation 0 C vddh charge pump is not in regulation or turned off inverting buck-boost power good vn_pg 1 C dcdc2 is in regulation 0 C dcdc2 is not in regulation or turned off vpos power good vpos_pg 1 C ldo1(vpos) is in regulation 0 C ldo1(vpos) is not in regulation or turned off vee power good vee_pg 1 C vee charge pump is in regulation 0 C vee charge pump is not in regulation or turned off not used n/a vneg power good vneg_pg 1 C ldo2(vneg) is in regulation 0 C ldo2(vneg) is not in regulation or turned off not used n/a (1) pg pin is pulled hi (hiz state) when vddh_pg = vpos_pg = vee_pg = vneg_pg = 1 revision and version control (revid) address C 0x10h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name revid[7:0] read/write r r r r r r r r reset value 0 1 0 0 0 e2 1 e2 0 e2 1 e2 field name bit definition revid[7:6] mjrev revid[5:4] mnrev revid[3:0] version 0100 0101 - tps65185 1p0 revid [7:0] 0101 0101 C tps65185 1p1 0110 0101 C tps65185 1p2 copyright ? 2011, texas instruments incorporated submit documentation feedback 41 product folder link(s): tps65185
package option addendum www.ti.com 11-apr-2013 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) op temp (c) top-side markings (4) samples tps65185rgzr active vqfn rgz 48 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 e ink tps65185 tps65185rgzt active vqfn rgz 48 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 e ink tps65185 tps65185rslr active vqfn rsl 48 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 tps 65185 TPS65185RSLT active vqfn rsl 48 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 tps 65185 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) multiple top-side markings will be inside parentheses. only one top-side marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire top-side marking for that device. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
package option addendum www.ti.com 11-apr-2013 addendum-page 2
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant tps65185rgzr vqfn rgz 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 q2 tps65185rgzt vqfn rgz 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 q2 tps65185rslr vqfn rsl 48 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 q2 TPS65185RSLT vqfn rsl 48 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 q2 package materials information www.ti.com 26-jan-2013 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) tps65185rgzr vqfn rgz 48 2500 367.0 367.0 38.0 tps65185rgzt vqfn rgz 48 250 210.0 185.0 35.0 tps65185rslr vqfn rsl 48 2500 367.0 367.0 38.0 TPS65185RSLT vqfn rsl 48 250 210.0 185.0 35.0 package materials information www.ti.com 26-jan-2013 pack materials-page 2

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